Computer Logic Design Help

Assign a delay to the gates; for example, take the smallest subdivision on the horizontal axis in the image, and say that the nand gates have this as propagation delay. Then, as the question states, twice this will be the delay of the xor/xnor gates.

Work out what is the starting value of F and G at the leftmost portion of the graph. Then, when A or B changes, you analyze the circuit's output using the propagation delays. For example (and assuming your minimized equations are right, I didn't check): at the start, F = 1 and G = 1. When A changes from 0 to 1, the effect will go through the gates. 1 time unit later, it will have gone through the nand gate at the top, causing F to change to 0; it will also have gone through the lower nand gate, changing one of the inputs to the lower xor. Another time unit later, the change in A will have affected the output of the top xor. And so on.

 

NAND delay is 1 unit of 5, XOR is 2 units.
I would figure I'm supposed to draw a graph of the outputs. Propagation delays are given so you can work out what the output would end up looking like. To make things clearer dosh the transition points so you would not mix it with settled time.
timing diagrams and state tables... my life is full of them haha