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Topics I've Started
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Z80: help identifying an algorithm
27 October 2013 - 08:10 AM
Code:
ROM:198D ; =============== S U B R O U T I N E ======================================= ROM:198D ROM:198D ROM:198D sub_198D: ; CODE XREF: ROM:1061p ROM:198D ; sub_1343+17p ... ROM:198D ld h, 1 ; 100h ROM:198F ld a, b ; a = b - c ROM:1990 sub c ROM:1991 jr nc, loc_199E ; if a xxx 0 goto loc ROM:1993 neg ; a = -a ROM:1995 srl a ; a >>= 1 (a /= 2) ROM:1997 ld c, a ; c = a ROM:1998 add a, b ; a += b ROM:1999 ld l, a ; a = (100h)[a] ROM:199A ld a, (hl) ROM:199B ld l, c ; a -= (100h)[c] ROM:199C sub (hl) ; alternatively, swap b and c, then do the below ROM:199D ret ROM:199E ; --------------------------------------------------------------------------- ROM:199E ROM:199E loc_199E: ; CODE XREF: sub_198D+4j ROM:199E srl a ; a >>= 1 (a /= 2) ROM:19A0 ld b, a ; b = a ROM:19A1 add a, c ; a += c ROM:19A2 ld l, a ; a = (100h)[a] ROM:19A3 ld a, (hl) ROM:19A4 ld l, b ; a -= (100h)[b] ROM:19A5 sub (hl) ROM:19A6 ret ROM:19A6 ; End of function sub_198D
Data at 100h:
ROM:0100 db 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1 ROM:0100 db 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 4, 4 ROM:0100 db 5, 5, 5, 5, 6, 6, 6, 7, 7, 7, 8, 8, 9, 9, 9, 0Ah, 0Ah ROM:0100 db 0Ah, 0Bh, 0Bh, 0Ch, 0Ch, 0Dh, 0Dh, 0Eh, 0Eh, 0Fh, 0Fh ROM:0100 db 10h, 10h, 11h, 11h, 12h, 12h, 13h, 13h, 14h, 14h, 15h ROM:0100 db 15h, 16h, 17h, 17h, 18h, 19h, 19h, 1Ah, 1Ah, 1Bh, 1Ch ROM:0100 db 1Ch, 1Dh, 1Eh, 1Eh, 1Fh, 20h, 21h, 21h, 22h, 23h, 24h ROM:0100 db 24h, 25h, 26h, 27h, 27h, 28h, 29h, 2Ah, 2Bh, 2Bh, 2Ch ROM:0100 db 2Dh, 2Eh, 2Fh, 30h, 31h, 31h, 32h, 33h, 34h, 35h, 36h ROM:0100 db 37h, 38h, 39h, 3Ah, 3Bh, 3Ch, 3Dh, 3Eh, 3Fh, 40h, 41h ROM:0100 db 42h, 43h, 44h, 45h, 46h, 47h, 48h, 49h, 4Ah, 4Bh, 4Ch ROM:0100 db 4Dh, 4Eh, 4Fh, 51h, 52h, 53h, 54h, 55h, 56h, 57h, 59h ROM:0100 db 5Ah, 5Bh, 5Ch, 5Dh, 5Fh, 60h, 61h, 62h, 64h, 65h, 66h ROM:0100 db 67h, 69h, 6Ah, 6Bh, 6Ch, 6Eh, 6Fh, 70h, 72h, 73h, 74h ROM:0100 db 76h, 77h, 79h, 7Ah, 7Bh, 7Dh, 7Eh, 7Fh, 81h, 82h, 84h ROM:0100 db 85h, 87h, 88h, 8Ah, 8Bh, 8Dh, 8Eh, 90h, 91h, 93h, 94h ROM:0100 db 96h, 97h, 99h, 9Ah, 9Ch, 9Dh, 9Fh, 0A0h, 0A2h, 0A4h ROM:0100 db 0A5h, 0A7h, 0A9h, 0AAh, 0ACh, 0ADh, 0AFh, 0B1h, 0B2h ROM:0100 db 0B4h, 0B6h, 0B7h, 0B9h, 0BBh, 0BDh, 0BEh, 0C0h, 0C2h ROM:0100 db 0C4h, 0C5h, 0C7h, 0C9h, 0CBh, 0CCh, 0CEh, 0D0h, 0D2h ROM:0100 db 0D4h, 0D5h, 0D7h, 0D9h, 0DBh, 0DDh, 0DFh, 0E1h, 0E2h ROM:0100 db 0E4h, 0E6h, 0E8h, 0EAh, 0ECh, 0EEh, 0F0h, 0F2h, 0F4h ROM:0100 db 0F6h, 0F8h, 0FAh, 0FCh, 0FEh
The given function takes b and c as input and produces a as output.
This is a sound driver, and at this point in the program I come across a structure like
db command_byte db unknown_parameter dw jump_table_target_1 dw jump_table_target_2 dw jump_table_target_3 ... jump_table_target_1: db command_bytes...
unknown_parameter is loaded into b and some other value is loaded into c; the result is the index into the jump table.
I am trying to determine one of the following two things:
1) Is unknown_parameter the size of the jump table? Or in other words, is b the upper bound of a?
2) What does this function do? I have no idea...
Thanks. -
Time Trax MD prototype dump
08 July 2013 - 01:07 PM
Hey guys, remember this, the unreleased Mega Drive port of the SNES game Time Trax that has new music by Tim Follin? Well some guys over at SegaAge managed to get the development files and provide a ROM at last, and yes it has the music intact! It also seems to be an unmodified ROM (from what I can tell by looking at the binary and starting the game). BIIIIIIIIIIIIG kudos to them for this, and I'll be sure to check out that (custom) sound driver! =P -
Questions about transistor-level microchip logic
17 May 2013 - 08:49 AM
So over the past few days I've been playing around with visual6502 and perfect6502, building this, which I intend to use to hook up several netlisted things together. I have two questions:
1) This first question involves understanding how visual6502/perfect6502 works. In perfect6502, there are three Boolean properties that a node can have: value (called state in visual6502), pullup, and pulldown. While the value/state holds whether or not the node is actually transmitting a high current, the function to set a node sets the pullup and pulldown properties to the requested state and its inverse, respectively, which are later used to set the value/state for the group of nodes controlled by the node we just set. The segdefs blob used to define nodes specifies the initial pullup property only (that is, pulldown is not set during initialization), and the initial value/state I set to zero. What I didn't understand was what pullup/pulldown represented. According to this, "a '+' [segdefs indicates set pullup on initialization to true] indicates a resistor is connected to the positive supply and will turn on attached gates if not shorted out." So given how setting a node works, should I assume that all node have a pullup resistor that is used to control the value? What about pulldown resistors; would those go on the negative edge? And what is the significance of having both pullup and pulldown set to false on initialization, since setNodes will always ensure pullup == !pulldown?
2) The second question involves what I am doing with visual6502/perfect6502: right now, data accesses are high-level and done whenever the high-level MMU, called monitor (and stored in runtime_init.go; the file should really be renamed monitor.go and the runtime.go to hlekernal.go) asks for a pin value. Of course this is in violation of 6502 timing diagrams. Furthermore, the monitor is using its own clone of the CPU clock, instead of being driven by the 6502's two-phase clock output. What I want to do is have the CPU, MMU, and other stuff run as separate coroutines. In Go, coroutines communicate with channels, which are mechanisms which send at most one value from a sender to a receiver. Channels block: if there is no sender, a receiver waits for one; if there is no receiver, a sender waits for one. I tried several different approaches that directly hook output/bidirectional pins to channels on node set value in an attempt to improve timing accuracy, but this just caused everything to deadlock. I determined there are several spurious reads and writes on pin nodes, so the question here is: is there a reliable way to determine which pin read/write is one that gets read by an external device? Or do I need to manually reconstruct the timing diagrams? Or am I doing it completely wrong and will need to find a different way to represent pins than channels? Or is timing accuracy not even possible on visual6502/perfect6502 because of how it sets groups of nodes/transistors at once?
Please let me know if any of this is unclear and I can try to clear it up. Thanks! -
IDA in wine stopping because of IDAPython
01 May 2013 - 10:41 AM
A while ago IDAPython started to fail to load because it couldn't perform an import site (done by Python initialization). I upgraded my IDAPython from the Python 2.6 version to the Python 2.7 version as Treeki suggested (it works for him/her) to see what was going on, and now it errors with
Traceback (most recent call last): File "C:\Python27\Lib\site.py", line 62, in <module> import os RuntimeError: unable to get file status from 'C:\Python27\Lib\os.py'
and closes IDA itself, making me unable to use it. The peculiar thing is that if I run the python command line executable from wine (either directly or thorugh wine cmd), everything just works (site imports fine and I can use python). I tried asking both #python and #winehq on Freenode multiple times but to no avail. I also tried looking into the site.py problem myself, noticing that it opens site.py fine and can run the import sys that comes immediately before the import os. Does anyone here know what is going on? Thanks.
Linux Mint 13 64-bit; wine 1.5.29 from the official wine PPA; IDA Pro Advanced 6.1; IDAPython 1.5.2 for IDA 6.1 for Python 2.7; Python 2.7.4 32-bit -
CSS: can I make nested list items justified with outer ones
28 April 2013 - 06:14 PM
HTML<ul> <li>foo <ul> <li>adsdas</li> <li>adsdas</li> <li>adsdas</li> <li>adsdas <ul> <li>abc</li> </ul> </li> <li>asdasd</li> </ul> </li> </ul>CSSul ul { list-style-position: inside; padding-left: 0px; }Or try a playground: http://jsfiddle.net/PGVnB/1/
I'd like the inner ul to also have its bullet justified with the leftmost margin of the text of the outer bullet, but no matter what I do (ul ul ul, ul ul li ul, ul li ul ul, ul li ul li ul, ul > ul, putting ul ul ul as a separate block, putting that separate block first, removing padding-left from that separate block), the third-level bullet refuses to align itself with the text of the second-level bullet, instead aligning to the bullet itself. That is to say, I want it to look like this:- level 1 - level 2 - level 2 - level 3 - level 2
I have a feeling list-style-position: inside is screwing up the browser's idea of where the left margin of the second level bullet is... Is there a solution to this problem that does not involve manually setting padding values and just using those (which is what Sik suggested)? Thanks.

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